Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased packing density, therefore increased net die per wafer (numbers of usable chips produced from a standard semiconductor wafer). To meet these requirements, semiconductor manufacturers have been forced to build new fabrication lines at the next generation process node (gate length). As the critical dimensions for these devices grow smaller, greater difficulties will be experienced in patterning these features using conventional photolithography.
Conventional photolithography methods used for pattern generation involve exposing a light-sensitive photoresist layer to a light source. The light from the source is modulated using a reticle, typically a chrome on quartz mask. The patterns formed on the reticle are transferred to the photoresist layer using typically visible or ultraviolet light. The areas so exposed are then developed (for positive photoresist) or, alternatively, the shaded areas are developed for negative type photoresist. The developed regions are then washed away and the remaining photoresist pattern used to provide an etching mask for the substrate.
One particularly difficult set of problems in the industry concerns the ability to form small “pillars” and/or “holes” in substrate. As is known to those having ordinary skill in the art; a laundry list of difficulties is encountered when smaller and smaller diameter holes and pillars are desired. This is especially the case for, for example, holes having diameters of about 200 nm or less. Another process difficulty currently encountered is the relative inability to form two different size holes (pillars) in the same process layer. This results in the need for altering the design of the substrate or increasing the number of process steps required to achieve the desired surface conformation (reducing throughput).
Thus, what is needed is an improved lithography process capable of overcoming some of these problems. Thus, the present invention provides improved fabrication and patterning methods useful in chip fabrication processes as well as other microscale substrate fabrication processes.